Verification

In our Electronic Design Services for SoC or FPGA designs, we employ state of the art verification techniques using tools provided by leading EDA companies such as Synopsys, Cadence and Mentor/Siemens including the following:

1. SystemC
2. Dynamic verification using VHDL, Verilog or SystemC with OVA Assertions
3. Constrained random verification using SystemVerilog, VHDL,SystemC, (VERA, Specman and e too)
   
4. Formal equivalence verification using Encounter, Formality or other
   
5. Acceleration of Verification, Emulation and production of pre-silicon prototype
6. Static timing analysis and timing closure
7. Formal Verification and Formal Equivalence Model Checking at every stage of design or translation of netlist
8. DRC and LVS
9. Scan test vectors, stuck at fault tests
   

We do the planning for the verification test bench, the verification suite, built-in self-test and built-in in-system live diagnosis/trouble-shooting silicon. We do all the coding. We select functional tests to augment wafer sorting scan tests when it makes sense.